World's first BitNet FPGA hardware accelerator · RISC-V + Anlogic FPGA + HarmonyOS LiteOS · 100% domestic · BOM <¥200
鸿源边缘AI推理加速器
World's first BitNet FPGA hardware accelerator · Full-stack self-designed RISC-V SoC
As of June 2026, no BitNet-specific FPGA/ASIC accelerators exist in global academic literature or patents. This project is the world’s first experimental platform to deploy BitNet b1.58 on FPGA hardware, with a 12–18 month first-mover advantage.
In traditional neural network inference, multipliers consume 70%+ of FPGA area and 60%+ of power. BitNet W1.58 constrains weights to {-1, 0, +1}, reducing all multiplication to addition/subtraction — enabling full Transformer inference on a 20K LUT low-end FPGA.
This is co-innovation across algorithm, architecture, and circuit layers simultaneously.
| Metric | Traditional FP16 | Hongyuan BitNet |
|---|---|---|
| Weight Precision | 16-bit float | 1.58-bit ternary {-1,0,+1} |
| Core Operation | MAC (multiply-accumulate) | Add/subtract (no multipliers) |
| Memory Footprint | Baseline | 16x compressed |
| FPGA Area | High | Low (20K LUT sufficient) |
| BOM Cost | ¥600+ (Jetson Nano) | <¥200 (Anlogic EG4X20) |
| Domestic Rate | 0% | 100% |
| Step | Validation | Result | Key Data |
|---|---|---|---|
| Step 1 | 16×16 BitNet Tile | ✅ 256/256 PASS | 8,192 cycles, 1,280 zero weights auto-skipped |
| Step 2 | 64-dim MLP Inference | ✅ Correct | 131,072 cycles, 4×4 Tile loop unrolling |
| Step 3 | QKV Projection | ✅ All Match | 24,576 cycles, 3× 16×16 GEMM |
| Step 4 | Single-Head Attention | ✅ 100% Match | 128 cycles, approx Softmax + V weighting |
| Step 5 | 2-Layer Transformer | ✅ All PASS | End-to-end, residual + LayerNorm |
| Step 6 | Inference Pipeline | ✅ State=DONE | Full flow QKV→ATTN→FFN→DONE |
All results from real Anlogic EG4X20 FPGA hardware · 256/256 exact match with software golden reference · 32KB firmware fully autonomous · No simulation data
🏆 2025 Shenzhen RISC-V & HarmonyOS Innovation Competition · Architecture Innovation Award